Complementary metal-oxide-semiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology has been used in digital logic circuits such as microprocessors, microcontrollers and static RAM. Recently, CMOS has received attention as a main-stream digital technology because of merits such as high degree integration, high performance, and low cost.
In CMOS, carriers are typically transported along a channel interface between gate dielectric and a substrate. Such a CMOS may be referred to as a surface-channel (SC) metal-oxide-semiconductor field-effect transistor (MOSFET), SC-N type metal-oxide-semiconductor (NMOS) or SC-P type metal-oxide-semiconductor (PMOS).
The channel interface may contain high-density traps, known as high density interface state, depending on the gate dielectric composition and process history. The high density interface state results in a relatively high flicker noise level. The flicker noise is also called low-frequency noise or 1/f noise where f is the frequency. High flicker noise is detrimental to most analog applications, in particular low-noise amplifiers.
Several methods have been used to reduce the flicker noise in analog CMOS. These methods include the use of “pure” oxide, appropriate annealing, incorporation of fluorine in the gate-oxide and at its interfaces, and/or the design of buried-channel (BC) MOSFETs, in particular BC PMOS. In a BCPMOS, for example, a large fraction of the current passes below the surface, reducing the rate of interface trapping and de-trapping which results in noise.
Despite the above methods to reduce flicker noise in CMOS, the noise level remains too high for specific analog applications such as low-noise amplifiers (LNA). For such applications, the junction field-effect transistor (JFET) has been used due to its very low noise level. The low noise is achieved by directing the current path deep below a surface thereof and minimizing the fraction of current reaching the interface with dielectric (typically oxide). In a JFET, a channel is almost totally buried and sandwiched between two junctions acting as a gate, thus reducing the fraction of current near a dielectric interface.
FIG. 1 is a schematic cross-section of a typical NJFET structure.
The basic principles of JFET operation may be best understood by considering an n-channel JFET, or NJFET, as illustrated in FIG. 1. While an n-channel JFET is chosen for illustration throughout the disclosure, the description applies equally to a p-type JFET by reversing dopant and voltage polarities. FIG. 1 also shows silicide blocking layers (SAB) that isolate junctions from each other. Isolation can also be achieved by well-known shallow-trench isolation (STI).
The JFET operates similarly to a MOSFET, except that in a JFET, a field in a channel is exerted by p-n junctions while in a MOSFET a field is exerted in a channel by applying a predetermined voltage on a conductor gate separated from the channel by an insulator (e.g., gate oxide).
As illustrated in FIG. 1, source 1 and drain 2 are typically formed by implanting a CMOS source and drain into substrate 3. The gate includes top gate 4 and bottom p-type junctions 5 which are connected to each other and to gate contacts 11 through a PWELL 9, as illustrated in the top-view in FIG. 2. The top gate (4) typically includes PMOS source/drain in a base CMOS technology, and a lightly-doped extension 7. An NWELL 8 connects contacts 10 to the isolating deep NWELL or n-buried layer (DNWELL or NBL) region 13. A region between the top and bottom gates is doped lightly to form an NJFET channel 6 with an optimized thickness and dopant concentration that allows turning the channel on and off by the top and bottom gates.
For example, multiple parallel JFET structures of the type in FIG. 1 are illustrated in FIG. 2.
FIG. 3 is a schematic cross-section of an NJFET without applied bias on a gate or a drain with respect to a channel. FIG. 4 is a schematic cross-sectional view on an NJFET operating at bias-voltage conditions where the JFET operates in saturation. FIG. 5 is a schematic cross-sectional view of an NJFET biased in the off-condition, i.e., pinched-off at the source.
In case of FIG. 3, a conducting channel depth is 2a-2xd, where 2a is a distance between gate-channel metallurgical junctions and xd is the thermal-equilibrium depletion width at each junction (assumed uniform for simplicity).
Channel resistance can be modulated by applying a reverse bias or moderate forward bias to the gate with respect to the channel. With zero gate voltage or moderately forward-biased gate, the depletion boundaries at the source, shown as dash-dot lines, expand only a little into the channel so that the channel remains fully conducting at the source. As the drain reverse-voltage is gradually increased under this gate-bias condition, the drain current initially increases linearly with increasing drain voltage. As the reverse drain-voltage further increases, however, the depletion regions at the drain expand further and eventually merge as illustrated in FIG. 4. The merger point is referred to as the pinch-off point P. When the depletion regions at the drain merge, the current saturates and the JFET is said to operate above pinch-off, similarly to a MOSFET operating above pinch-off.
Applying a reverse-voltage on the gate reduces the conducting channel-thickness at both the source and drain, thus increasing the channel resistance and reducing the current. When the top and bottom depletion regions spread throughout the channel at the source, pinching-off the channel at the source as illustrated in FIG. 5, the drain current drops to a very low value and the channel is turned-off. The gate voltage at pinch-off at the source, VP, depends on channel concentration and thickness. The pinch-off voltage VP of a JFET is directly related to its threshold voltage VT.
Fabricating steps of a typical JFET are similar to those of a standard medium to high-voltage CMOS structure, except for the addition of an extra mask to form the JFET channel 6, bottom-gate 5, and p-type adjustment near the surface 7 in FIG. 1. Implantation of the bottom gate, JFET channel, and an eventual dopant near the surface are done during the same masking step. Regions 4 and 7 merge as one p-type gate region in FIG. 1. The PSD part of the top gate of an n-channel JFET is formed at the same time as the PMOS source and drain in CMOS. The NJFET source and drain contacts are formed at the same time as the NMOS source and drain in CMOS. The CMOS NWELL 8 constitutes the connection between n+ contacts 10 and deep NWELL (DNWELL) or N-buried layer (NBL) 13, as illustrated in FIG. 1. The CMOS PWELL 9 ensures the connection of the top gate 4 and bottom gate 5, and the connection of top p-contact 11 and bottom gate 5. Thus, the NJFET requires only one additional mask to a base CMOS process. Such a related fabricating method is presently adopted in high-performance analog technologies.
The JFET, however, has draw backs of large size and limited current-carrying capability while it exhibits a very low flicker-noise level. The channel concentration must satisfy a low pinch-voltage, typically in the range 1.0-2.0V, and a related optimized drain current. Once the pinch-voltage is fixed, the combination of channel depth and concentration are also fixed, determining the drain current.
For a JFET with top and bottom gates, the channel resistance, RCh, per unit width is given as the following Equation 1:
                                          R            Ch                    =                                                    ρ                _                            ⁢                              L                S                                      =                                                                                ρ                    _                                    ⁢                                                                          ⁢                  L                                                  2                  ⁢                                      W                    ⁡                                          (                                              a                        -                                                  x                          d                                                                    )                                                                                  ⁢                                                          ⁢              Ohm              ⁢                              -µm                                                    ,                            Eq        .                                  ⁢        1            
where ρ is the effective channel resistivity given as follows in Equation 2:
                                          ρ            _                    =                                    1                              q                ⁢                                                                  ⁢                                                                            μ                      n                                        ⁢                                          N                      D                                                        _                                                      ⁢                                                  ⁢            Ohm            ⁢                          -cm                                      ,                            Eq        .                                  ⁢        2            
L is the channel length, and S the cross-sectional area given by 2W(a-xd). a is half the distance between metallurgical junctions, and xd the gate-channel junction depletion-width, as illustrated in FIG. 3. The total pinch-voltage (including the built-in voltage) is as follows in Equation 3:
                                          V            P                    =                                                    q                ⁢                                                                  ⁢                                                      N                    D                                    _                                ⁢                                  a                  2                                                            2                ⁢                                  ɛ                  Si                                                      ⁢            V                          ,                            Eq        .                                  ⁢        3            
Where ND is the effective channel concentration and εSi the silicon permittivity (=11.7×8.86×10−14 F/cm). It can be seen from the above equations that, for a given channel depth 2a, when Vp is fixed, ND and thus RCh are also fixed. Also, because of the requirement on low channel concentration (low pinch-voltage), a minimum length L is needed to avoid short-channel effects.
In summary, the JFET suffers from its large size and limited current-carrying capability.